Invention Grant
- Patent Title: Mitigating thermal impacts on adjacent stacked semiconductor devices
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Application No.: US17962258Application Date: 2022-10-07
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Publication No.: US11984427B2Publication Date: 2024-05-14
- Inventor: Sui Chi Huang
- Applicant: Lodestar Licensing Group LLC
- Applicant Address: US IL Evanston
- Assignee: Lodestar Licensing Group LLC
- Current Assignee: Lodestar Licensing Group LLC
- Current Assignee Address: US IL Evanston
- Agency: Holland & Hart LLP
- The original application number of the division: US16871490 2020.05.11
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/67 ; H01L23/34 ; H01L23/40

Abstract:
A semiconductor device assembly and associated methods are disclosed herein. The semiconductor device assembly includes (1) a substrate having a first side and a second side opposite the first side; (2) a first set of stacked semiconductor devices at the first side of the substrate; (3) a second set of stacked semiconductor devices adjacent to one side of the first set of stacked semiconductor devices; (4) a third set of stacked semiconductor devices adjacent to an opposite side of the first set of stacked semiconductor devices; and (5) a temperature adjusting component at the second side and aligned with the second set of stacked semiconductor devices. The temperature adjusting component is positioned to absorb the thermal energy and thereby thermally isolate the second set of stacked semiconductor devices from the first set of stacked semiconductor devices.
Public/Granted literature
- US20230033685A1 MITIGATING THERMAL IMPACTS ON ADJACENT STACKED SEMICONDUCTOR DEVICES Public/Granted day:2023-02-02
Information query
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