Invention Grant
- Patent Title: Method for packaging semiconductor, semiconductor package structure, and package
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Application No.: US17372530Application Date: 2021-07-12
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Publication No.: US11990451B2Publication Date: 2024-05-21
- Inventor: Jie Liu , Zhan Ying
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: CN 1910982076.1 2019.10.16
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/78 ; H01L25/00 ; H01L25/065

Abstract:
Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and filling an insulating dielectric in a gap between a sidewall of the groove and the semiconductor die stack to form an insulating dielectric layer covering an upper surface of the semiconductor die stack to seal up the semiconductor die stack so as to form the semiconductor package structure.
Public/Granted literature
- US11929350B2 Method for packaging semiconductor, semiconductor package structure, and package Public/Granted day:2024-03-12
Information query
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