Invention Grant
- Patent Title: Multi-level spin logic
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Application No.: US17152552Application Date: 2021-01-19
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Publication No.: US11990899B2Publication Date: 2024-05-21
- Inventor: Sasikanth Manipatruni , Ian A. Young , Dmitri E. Nikonov , Uygar E. Avci , Patrick Morrow , Anurag Chaudhry
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- Main IPC: H03K19/173
- IPC: H03K19/173 ; H03K19/00 ; H03K19/18 ; H10N50/85 ; H10N52/00 ; H10N52/80

Abstract:
Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.
Public/Granted literature
- US20210143819A1 MULTI-LEVEL SPIN LOGIC Public/Granted day:2021-05-13
Information query
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