Invention Grant
- Patent Title: Multiple-requestor memory access pipeline and arbiter
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Application No.: US17734174Application Date: 2022-05-02
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Publication No.: US12001351B2Publication Date: 2024-06-04
- Inventor: Abhijeet Ashok Chachad , David Matthew Thompson
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Brian D. Graham; Frank D. Cimino
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F12/08
Abstract:
In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The memory system can include a pipeline for accessing data stored in one of the caches. Requestors can access the data stored in one of the caches by sending requests at a same time that can be arbitrated by the pipeline.
Public/Granted literature
- US20220261360A1 MULTIPLE-REQUESTOR MEMORY ACCESS PIPELINE AND ARBITER Public/Granted day:2022-08-18
Information query
