A memory controller controls access to a Synchronous Dynamic Random Access Memory (SDRAM) including banks. The memory controller includes: a receiver that receives a memory access request from an access master; a selector that selects one of a first issue mode and a second issue mode each related to command issuing; and an issuer that issues a command sequence to the SDRAM in response to the memory access request, in accordance with the one of the first issue mode and the second issue mode which is selected by the selector. The first issue mode is a mode in which an activation command for activating a bank among the banks is issued in continuous clock cycles without dividing the activation command, the activation command being included in the command sequence. The second issue mode is a mode in which the activation command is divided and issued in non-continuous clock cycles.