Invention Grant
- Patent Title: Determine link startup sequence (LSS) type using reference clock frequency and attribute
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Application No.: US17875054Application Date: 2022-07-27
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Publication No.: US12001711B2Publication Date: 2024-06-04
- Inventor: Rotem Sela , Shemmer Choresh
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: PATTERSON + SHERIDAN, LLP
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
The present disclosure generally relates to utilizing the host clock signal frequency to determine whether to operate in the default pulse width modulation (PWM) link startup sequence (LSS), be changed to high speed (HS) LSS by a host device capable of operating in either PWM LSS or HS LSS, or ignore the data storage device attributes of operating in PWM LSS and instead operate according to HS LSS. In so doing, the data storage device is adaptable to work with older generation UFS host devices as well as current and future generation UFS host devices.
Public/Granted literature
- US20230035584A1 Determine Link Startup Sequence (LSS) Type Using Reference Clock Frequency And Attribute Public/Granted day:2023-02-02
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