Invention Grant
- Patent Title: Analog centric current modeling within a digital testbench in mixed-signal verification
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Application No.: US15658308Application Date: 2017-07-24
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Publication No.: US12001770B2Publication Date: 2024-06-04
- Inventor: Vijay Akkaraju , David Francis Cronauer
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: G06F30/367
- IPC: G06F30/367 ; G06F30/33 ; G06F30/3308 ; G06F30/3312 ; G06F30/38

Abstract:
A method includes operating a digital simulator to mimic loading effects of digital circuit blocks of a circuit design on analog circuit blocks of the circuit design. The digital simulator sets a current signal timing and a current level value at an analog/digital boundary between the digital circuit aspects and the analog circuit aspects. The analog simulator is operated to apply the current signal timing and the current level value to simulate the analog circuit blocks.
Public/Granted literature
- US20180129767A1 ANALOG CENTRIC CURRENT MODELING WITHIN A DIGITAL TESTBENCH IN MIXED-SIGNAL VERIFICATION Public/Granted day:2018-05-10
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