Invention Grant
- Patent Title: Vertical field effect transistor with crosslink fin arrangement
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Application No.: US18179556Application Date: 2023-03-07
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Publication No.: US12002856B2Publication Date: 2024-06-04
- Inventor: Indira Seshadri , Ruilong Xie , Chen Zhang , Ekmini Anuja De Silva
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Kimberly Zillig
- The original application number of the division: US17125850 2020.12.17
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L21/308 ; H01L29/78

Abstract:
A method of forming a semiconductor structure includes forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate. First sidewall image transfer spacers are formed on opposing longitudinal sidewalls of each mandrel in the first array of mandrels. A second array of mandrels is formed on the hardmask layer. Each mandrel in the second array of mandrels is laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers. Second sidewall image transfer spacers are formed on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels. Portions of the second sidewall image transfer spacers are selectively removed to define a crosslink fin pattern to be transferred to the semiconductor substrate.
Public/Granted literature
- US20230207632A1 VERTICAL FIELD EFFECT TRANSISTOR WITH CROSSLINK FIN ARRANGEMENT Public/Granted day:2023-06-29
Information query
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