A display device includes an N-phase level shifter configured to receive an output cancellation signal, a first reference signal, and a second reference signal from a timing controller, and to output N sensing clock signals to a gate driver, and the gate driver configured to receive the N sensing clock signals from the N-phase level shifter, and to output N sensing output signals to first to n-th gate lines, wherein the N-phase level shifter is configured to receive the output cancellation signal having a number of pulses during a blank period, and the a is at least two.