Invention Grant
- Patent Title: Semiconductor device with reduced critical dimensions
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Application No.: US17510918Application Date: 2021-10-26
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Publication No.: US12009212B2Publication Date: 2024-06-11
- Inventor: Kuo-Hui Su
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agent Xuan Zhang
- The original application number of the division: US16440354 2019.06.13
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/02 ; H01L21/3115

Abstract:
A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.
Information query
IPC分类: