Invention Grant
- Patent Title: Method of making a silicon on insulator wafer
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Application No.: US17222554Application Date: 2021-04-05
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Publication No.: US12009252B2Publication Date: 2024-06-11
- Inventor: Alexander Yuri Usenko
- Applicant: Alexander Yuri Usenko
- Applicant Address: US MO Belton
- Assignee: Alexander Yuri Usenko
- Current Assignee: Alexander Yuri Usenko
- Current Assignee Address: US MO Belton
- Main IPC: H01L21/762
- IPC: H01L21/762

Abstract:
A process for making silicon on insulator wafer by bond and etch back—BESOI. A boron etch stop is formed by BF2+ ion implantation followed by solid phase epitaxy—SPE. Fluorine getters metals for OISF immunity of the final wafer. SPE activates boron above solubility limit thus facilitates high etch selectivity. Future cap silicon film is epitaxially grown over the boron etch stop at temperature that limits boron diffusion and boron deactivation. High temperature hydrogen bake step in epitaxy is replaced with Siconi of similar low temperature process. Buried oxide is thermally grown from portion of cap silicon layer at temperature limiting Boron diffusion and deactivation. Thus, SOI wafer design is the same as in layer transfer process—bonding interface is at the bottom interface of BOX; properties of final SOI wafer are equal to SOI made by layer transfer process—including cap silicon layer thickness variation, and OISF defect count. Advantage over the layer transfer—this process does not require non-standard equipment. Standard processing tool set readily available at semiconductor foundries is sufficient to run this process. Foundries can use this process for in house SOI wafer manufacturing.
Public/Granted literature
- US20220319912A1 METHOD OF MAKING A SILICON ON INSULATOR WAFER Public/Granted day:2022-10-06
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