Invention Grant
- Patent Title: Separation of parity columns in bit-flip decoding of low-density parity-check codes with pipelining and column parallelism
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Application No.: US17556080Application Date: 2021-12-20
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Publication No.: US12014071B2Publication Date: 2024-06-18
- Inventor: Eyal En Gad , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Yoav Weinberg
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Greenberg Traurig
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F3/06
Abstract:
A memory device having a bit-flipping decoder. The decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. The decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.
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