Disclosed herein are apparatus, method, and computer-readable storage device embodiments for implementing deconvolution via a set of convolutions. An embodiment includes a convolution processor that includes hardware implementing logic to perform at least one algorithm comprising a convolution algorithm. The at least one convolution processor may be further configured to perform operations including performing a first convolution and outputting a first deconvolution segment as a result of the performing the first convolution. The at least one convolution processor may be further configured to perform a second convolution and output a second deconvolution segment as a result of the performing the second convolution. According to some embodiments, the at least one convolution processor may be further configured to perform at least one further convolution to generate at least one further deconvolution segment, until a number of deconvolution segments output by the convolution processor reaches a deconvolution-size-value.