Invention Grant
- Patent Title: Method of semiconductor overlay measuring and method of semiconductor structure manufacturing
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Application No.: US17233560Application Date: 2021-04-19
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Publication No.: US12014961B2Publication Date: 2024-06-18
- Inventor: Kai-Ping Chan , Tsu-Wen Huang , Kai Lee
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: CKC & Partners Co., LLC
- Main IPC: H01L21/66
- IPC: H01L21/66 ; G03F7/00 ; G06T7/00 ; H01L21/768 ; H01L23/544 ; H01L49/02 ; H10B12/00

Abstract:
A method of semiconductor overlay measuring includes following operations. Provide a test substrate. Conductive structures are located in the test substrate and exposed from a top surface of the test substrate. Positioning the test substrate to a standard position and capturing a first image of the top surface of the test substrate. Mark first marks corresponding to the exposed conductive structures on the first image. Form a test capping layer with capacitor openings on the top surface of the test substrate. Move the test substrate to the standard position and capturing a second image of a top surface of the test capping layer. Identify the capacitor openings on the second image with second marks. Compare the first marks with the second marks to determine a position offset between the test substrate and the test capping layer.
Public/Granted literature
- US20220336292A1 METHOD OF SEMICONDUCTOR OVERLAY MEASURING AND METHOD OF SEMICONDUCTOR STRUCTURE MANUFACTURING Public/Granted day:2022-10-20
Information query
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