Invention Grant
- Patent Title: Deep trench capacitor including stress-relief voids and methods of forming the same
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Application No.: US17458706Application Date: 2021-08-27
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Publication No.: US12015050B2Publication Date: 2024-06-18
- Inventor: Fu-Chiang Kuo
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsinchu
- Agency: The Marbury Law Group, PLLC
- Main IPC: H01G4/35
- IPC: H01G4/35 ; H01L23/532 ; H01L49/02

Abstract:
A deep trench is formed in a substrate. A layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers is formed over the substrate. The layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench. A dielectric fill material layer including a dielectric fill material is formed in the cavity and over the substrate. The dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity. The void may expand or shrink under stress during subsequently handling of a deep trench capacitor including the layer stack to absorb mechanical stress and to increase mechanical stability of the deep trench capacitor.
Public/Granted literature
- US20230069538A1 DEEP TRENCH CAPACITOR INCLUDING STRESS-RELIEF VOIDS AND METHODS OF FORMING THE SAME Public/Granted day:2023-03-02
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