Invention Grant
- Patent Title: Memory array architecture having sensing circuitry to drive two matrices for higher array efficiency
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Application No.: US17842492Application Date: 2022-06-16
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Publication No.: US12020745B2Publication Date: 2024-06-25
- Inventor: Hongmei Wang , Soichi Sugiura
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G11C11/40
- IPC: G11C11/40 ; G11C11/4091 ; G11C11/4097
Abstract:
An apparatus may include a first matrix comprising a first plurality of digit lines, a second matrix comprising a second plurality of digit lines, a plurality of sense amplifiers, and a plurality of selector circuits. Each selector circuit of the plurality of selector circuits may be configured to selectively couple a respective sense amplifier to either a first digit line of the first plurality of digit lines or a second digit line of the second plurality of digit lines.
Public/Granted literature
- US20230410895A1 MEMORY ARRAY ARCHITECTURE HAVING SENSING CIRCUITRY TO DRIVE TWO MATRICES FOR HIGHER ARRAY EFFICIENCY Public/Granted day:2023-12-21
Information query
