- Patent Title: Trench etching process for photoresist line roughness improvement
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Application No.: US18054348Application Date: 2022-11-10
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Publication No.: US12020933B2Publication Date: 2024-06-25
- Inventor: Sheng-Lin Hsieh , I-Chih Chen , Ching-Pei Hsieh , Kuan Jung Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY, LIMITED
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,TSMC NANJING COMPANY, LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,TSMC NANJING COMPANY, LIMITED
- Current Assignee Address: TW Hsinchu; CN Nanjing
- Agency: Hauptman Ham, LLP
- Priority: CN 1911270313.8 2019.12.11
- Main IPC: H01L21/027
- IPC: H01L21/027 ; H01L21/033 ; H01L21/768

Abstract:
A method of forming a semiconductor device structure includes forming a resist structure over a substrate, the resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth sidewalls of the trench, and the hydrogen plasma treatment is performed at a temperature ranging from about 200° C. to about 600° C. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.
Public/Granted literature
- US20230060956A1 TRENCH ETCHING PROCESS FOR PHOTORESIST LINE ROUGHNESS IMPROVEMENT Public/Granted day:2023-03-02
Information query
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