Invention Grant
- Patent Title: Overlay mark forming Moire pattern, overlay measurement method using same, and manufacturing method of semiconductor device using same
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Application No.: US18314433Application Date: 2023-05-09
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Publication No.: US12021040B2Publication Date: 2024-06-25
- Inventor: Hyun Chul Lee , Hyun Jin Chang , Sung Hoon Hong , Young Je Woo
- Applicant: AUROS TECHNOLOGY, INC.
- Applicant Address: KR Hwaseong-si
- Assignee: AUROS TECHNOLOGY, INC.
- Current Assignee: AUROS TECHNOLOGY, INC.
- Current Assignee Address: KR Hwaseong-si
- Agency: NKL LAW
- Agent Jae Youn Kim
- Priority: KR 20220008304 2022.01.20
- Main IPC: H01L23/544
- IPC: H01L23/544 ; G03F1/42 ; G03F7/00 ; G03F7/20 ; H01L21/66

Abstract:
An overlay mark, an overlay measurement method using the same, and a manufacturing method of a semiconductor device using the same are provided. The overlay mark is for measuring an overlay based on an image, is configured to determine a relative misalignment between at least two pattern layers, and includes first to fourth overlay marks. The first overlay mark has a pair of first Moire patterns disposed on a center portion of the overlay mark. The second overlay mark has a pair of second Moire patterns disposed so as to face each other with the first Moire patterns interposed therebetween. The third overlay mark has a pair of third Moire patterns disposed on a first diagonal line with the first Moire patterns interposed therebetween. The fourth overlay mark has a pair of fourth Moire patterns disposed on a second diagonal line with the first Moire patterns interposed therebetween.
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