Invention Grant
- Patent Title: Redistribution layer (RDL) layouts for integrated circuits
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Application No.: US18362730Application Date: 2023-07-31
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Publication No.: US12021054B2Publication Date: 2024-06-25
- Inventor: Cheng-Yuan Li , Kuo-Cheng Lee , Yun-Wei Cheng , Yen-Liang Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- The original application number of the division: US15965116 2018.04.27
- Main IPC: H01L23/00
- IPC: H01L23/00
Abstract:
Redistribution layers of integrated circuits include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.
Public/Granted literature
- US20230378116A1 Redistribution Layer (RDL) Layouts for Integrated Circuits Public/Granted day:2023-11-23
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