Invention Grant
- Patent Title: Reducing keep-out-zone area for a semiconductor device
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Application No.: US17028484Application Date: 2020-09-22
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Publication No.: US12021060B2Publication Date: 2024-06-25
- Inventor: Kevin Du , Hope Chiu , Zengyu Zhou , Alex Zhang , Vincent Jiang , Shixing Zhu , Paul Qu , Yi Su , Rui Yuan
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Morgan, Lewis & Bockius LLP
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L21/48 ; H01L23/00 ; H01L23/31 ; H01L25/00 ; H01L25/065
Abstract:
A packaged semiconductor includes a substrate and a first component disposed on the substrate. The package includes an underfill that is dispensed under and around the first component. The package also includes a second component disposed on the substrate adjacent to the first component that provides a border to the underfill.
Public/Granted literature
- US20220093559A1 REDUCING KEEP-OUT-ZONE AREA FOR A SEMICONDUCTOR DEVICE Public/Granted day:2022-03-24
Information query
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