Invention Grant
- Patent Title: Selective liner on backside via and method thereof
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Application No.: US18358576Application Date: 2023-07-25
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Publication No.: US12021119B2Publication Date: 2024-06-25
- Inventor: Lin-Yu Huang , Li-Zhen Yu , Chia-Hao Chang , Cheng-Chi Chuang , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- The original application number of the division: US16944263 2020.07.31
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L23/528 ; H01L29/06 ; H01L29/78

Abstract:
A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.
Public/Granted literature
- US20230369401A1 SELECTIVE LINER ON BACKSIDE VIA AND METHOD THEREOF Public/Granted day:2023-11-16
Information query
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