Invention Grant
- Patent Title: Method for semiconductor device interface circuitry functionality and compliance testing
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Application No.: US17122202Application Date: 2020-12-15
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Publication No.: US12025663B2Publication Date: 2024-07-02
- Inventor: Howard H. Roberts, Jr. , LeRoy Growt , Thomas Schoen
- Applicant: CELERINT, LLC
- Applicant Address: US NY New York
- Assignee: CELERINT, LLC
- Current Assignee: CELERINT, LLC
- Current Assignee Address: US NY New York
- Agency: GREENBLUM & BERNSTEIN, P.L.C.
- Main IPC: G01R31/319
- IPC: G01R31/319 ; G01R31/3183

Abstract:
A method is provided for testing the functionality of a device under test interface circuitry located between automated testing equipment (ATE) and a device under test (DUT). The method includes disconnecting the device under test from the device under test interface circuitry, utilizing a Source Measurement Unit (SMU) that generates and measures voltage and current and uses force and sense lines, and testing a switch located in the device under test interface circuitry using a two-state alarm process. The method also includes applying a voltage using the a voltage source measurement device in a first state in which force and sense lines of the voltage source measurement device are connected in the device under test interface circuitry. The method further includes detecting whether an alarm signal due to an open circuit has been activated, and determining that the switch being tested in the device under test interface circuitry is operating properly by the absence of the alarm signal being activated.
Public/Granted literature
- US20210181252A1 METHOD FOR SEMICONDUCTOR DEVICE INTERFACE CIRCUITRY FUNCTIONALITY AND COMPLIANCE TESTING Public/Granted day:2021-06-17
Information query
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