Quadrature clock generation circuits and techniques are disclosed. An example quadrature clock generator includes an in-phase (I) clock generation circuit to generate an I clock signal based on a reference clock signal, the I clock signal and the reference clock signal each having a first frequency, a quadrature phase (Q) clock generation circuit to generate a Q clock signal based on the reference clock signal, a rise time control signal, and a fall time control signal, the Q clock signal having the first frequency, and a control circuit to generate the rise time control signal and the fall time control signal based on the I clock signal and the Q clock signal.