A flash memory physical interface in a host device may be configured based on a selection signal indicating whether a flash memory system is a first type or a second type. Based on the selection signal, either a first differential memory data signal input of driver circuitry or a second differential memory data signal input of the driver circuitry may be coupled to a differential data input of the flash memory system. Based on the selection signal, a differential data output of the flash memory system may be coupled to either a first differential memory data signal output of receiver circuitry or a second differential memory data signal output of the receiver circuitry.