Invention Grant
- Patent Title: Programming delay scheme for a memory sub-system based on memory reliability
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Application No.: US17752579Application Date: 2022-05-24
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Publication No.: US12027210B2Publication Date: 2024-07-02
- Inventor: Yu-Chung Lien , Zhenming Zhou
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/08 ; G11C16/26 ; G11C16/32

Abstract:
A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device. The processing device is further to determine a value of a metric reflecting reliability of a subset of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a programming operation with respect to the subset of memory cells. The programming operation includes the delay between a first pass of the programming operation and a second pass of the programming operation.
Public/Granted literature
- US20230410914A1 PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY Public/Granted day:2023-12-21
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