Invention Grant
- Patent Title: Packaged semiconductor device with electroplated pillars
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Application No.: US17404918Application Date: 2021-08-17
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Publication No.: US12027483B2Publication Date: 2024-07-02
- Inventor: Arvin Cedric Quiambao Mallari , Maricel Fabia Escano , Armando Tresvalles Clarina, Jr. , Jovenic Romero Esquejo
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Dawn Jos; Frank D. Cimino
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L23/495

Abstract:
In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.
Public/Granted literature
- US20210375808A1 PACKAGED SEMICONDUCTOR DEVICE WITH ELECTROPLATED PILLARS Public/Granted day:2021-12-02
Information query
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