Invention Grant
- Patent Title: Methods of forming stacked integrated circuits using selective thermal atomic layer deposition on conductive contacts and structures formed using the same
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Application No.: US17470630Application Date: 2021-09-09
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Publication No.: US12027488B2Publication Date: 2024-07-02
- Inventor: Mike Breeden , Victor Wang , Andrew Kummel , Ming-Jui Li , Muhannad Bakir , Jonathan Hollin , Nyi Myat Khine Linn , Charles H. Winter
- Applicant: The Regents of the University of California , Georgia Tech Research Corporation , Wayne State University
- Applicant Address: US CA Oakland
- Assignee: The Regents of the University of California,Wayne State University,Georgia Tech Research Corporation
- Current Assignee: The Regents of the University of California,Wayne State University,Georgia Tech Research Corporation
- Current Assignee Address: US CA Oakland; US MI Detroit; US GA Atlanta
- Agency: Stanek Lemon Crouse & Meeks, PA
- Main IPC: H01L23/00
- IPC: H01L23/00
Abstract:
Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.
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