Invention Grant
- Patent Title: Fanout integration for stacked silicon package assembly
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Application No.: US16672802Application Date: 2019-11-04
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Publication No.: US12027493B2Publication Date: 2024-07-02
- Inventor: Jaspreet Singh Gandhi , Suresh Ramalingam
- Applicant: XILINX, INC.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/56 ; H01L21/60 ; H01L23/00

Abstract:
A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.
Public/Granted literature
- US20210134757A1 FANOUT INTEGRATION FOR STACKED SILICON PACKAGE ASSEMBLY Public/Granted day:2021-05-06
Information query
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