Invention Grant
- Patent Title: Three-dimensional stacking semiconductor assemblies with near zero bond line thickness
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Application No.: US17832019Application Date: 2022-06-03
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Publication No.: US12027498B2Publication Date: 2024-07-02
- Inventor: Owen R. Fay
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- The original application number of the division: US16774900 2020.01.28
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/683 ; H01L23/00 ; H01L23/498 ; H01L23/522 ; H01L23/528 ; H01L23/532 ; H01L25/00

Abstract:
Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.
Public/Granted literature
- US20220293569A1 THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES WITH NEAR ZERO BOND LINE THICKNESS Public/Granted day:2022-09-15
Information query
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