Invention Grant
- Patent Title: Method of manufacturing a heterostructure or a stacked semiconductor structure having a silicon-germanium interface
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Application No.: US17850310Application Date: 2022-06-27
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Publication No.: US12027592B2Publication Date: 2024-07-02
- Inventor: Martin Christopher Holland , Blandine Duriez
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: STUDEBAKER & BRACKETT PC
- The original application number of the division: US15908135 2018.02.28
- Main IPC: H01L29/167
- IPC: H01L29/167 ; H01L21/02 ; H01L29/08 ; H01L29/10 ; H01L29/66 ; H01L29/78 ; H01L29/16 ; H01L29/161 ; H01L29/165 ; H01L29/417
Abstract:
A field effect transistor includes a channel made of germanium and a source/drain portion. The source/drain portion includes a germanium layer, an interfacial epitaxial layer over the germanium layer, a semiconductor layer over the interfacial epitaxial layer, and a conducting layer over the semiconductor layer. The interfacial epitaxial layer contains germanium and an element from the semiconductor layer and has a thickness in a range from about 1 nm to about 3 nm.
Public/Granted literature
- US20220328633A1 GE BASED SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME Public/Granted day:2022-10-13
Information query
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