Invention Grant
- Patent Title: Method of manufacturing wiring substrate
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Application No.: US18128779Application Date: 2023-03-30
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Publication No.: US12028967B2Publication Date: 2024-07-02
- Inventor: Mao-Feng Hsu , Zhi-Hong Yang
- Applicant: Avary Holding(Shenzhen)Co., Ltd. , HongQiSheng Precision Electronics(QinHuangdao)Co., Ltd. , Garuda Technology Co., Ltd.
- Applicant Address: CN Shenzhen
- Assignee: Avary Holding(Shenzhen)Co., Ltd.,HongQiSheng Precision Electronics(QinHuangdao)Co., Ltd.,Garuda Technology Co., Ltd.
- Current Assignee: Avary Holding(Shenzhen)Co., Ltd.,HongQiSheng Precision Electronics(QinHuangdao)Co., Ltd.,Garuda Technology Co., Ltd.
- Current Assignee Address: CN Shenzhen; CN Hebei Province; TW New Taipei
- Agency: MUNCY, GEISSLER, OLDS & LOWE, P.C.
- Priority: CN 2111238769.3 2021.10.25
- The original application number of the division: US17457025 2021.11.30
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H05K3/46

Abstract:
A wiring substrate includes a first insulating layer with a first opening, a second insulating layer with a second opening, a high-frequency wiring layer, a first wiring layer, a second wiring layer, and a plurality of conductive pillars. The high-frequency wiring layer including a high-frequency trace is sandwiched between the first insulating layer and the second insulating layer. The first opening and the second opening expose two sides of the high-frequency trace respectively. The high-frequency trace has a smooth surface which is not covered by the first insulating layer and the second insulating layer and has the roughness ranging between 0.1 and 2 μm. The first insulating layer and the second insulating layer are all located between the first wiring layer and the second wiring layer. The conductive pillars are disposed in the second insulating layer and connected to the high-frequency trace.
Public/Granted literature
- US20230239998A1 METHOD OF MANUFACTURING WIRING SUBSTRATE Public/Granted day:2023-07-27
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