An interface circuit includes an operation controller that controls an operation state of the interface circuit; a converter that outputs divided print data signals, each divided print data signal of the divided print data signals having a predetermined bit width; a storage that stores the divided print data signals. The interface circuit includes a data controller that controls an order of writing of the divided print data signals into the storage and reading of the divided print data signals from the storage; a logical arithmetic module that performs logical arithmetic operations based on the divided print data signal and a history pulse signal and outputs a history print data signal that defines heat generating time periods of dots corresponding to print lines to be printed; and a conversion clock synchronizer that outputs the history print data signal in synchronization with a driving signal for a thermal head.