Invention Grant
- Patent Title: Non-volatile memory with reduced word line switch area
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Application No.: US17957424Application Date: 2022-09-30
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Publication No.: US12032837B2Publication Date: 2024-07-09
- Inventor: Yuki Mizutani , Kazutaka Yoshizawa , Kiyokazu Shishido , Eiichi Fujikura
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Austin
- Agency: Vierra Magen Marcus LLP
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.
Public/Granted literature
- US20240111440A1 NON-VOLATILE MEMORY WITH REDUCED WORD LINE SWITCH AREA Public/Granted day:2024-04-04
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