A display panel and a drive method therefor, where when a gate electrode drive circuit (100) scans pixels line-by-line, a drive chip (300) controls a clock signal end to input a clock control signal (CK) into the gate electrode drive circuit (100), which causes a gate electrode scan signal (G(n)) to be output by the gate electrode drive circuit (100), and a data signal (Vd) output by a data signal end is controlled to be written to a corresponding row of pixel circuits (200). Where an active level period of the clock control signal (CK) falls within an active level period of the data signal (Vd), and a start time for the active level period of the data signal (Vd) is at least 1-2 μs earlier than a start time for the active level period of the clock control signal (CK).