A memory device and an operation method thereof are provided. The operation method comprises: in performing a multiply accumulate (MAC) operation, inputting a plurality of inputs into a plurality of memory cells via a plurality of first signal lines; outputting a plurality of cell currents from the memory cells to a plurality of second signal lines based on a plurality of weights of the memory cells; summing the cell currents on each of the second signal lines into a plurality of signal line currents: summing the signal line currents into a global signal line current: and converting the global signal line current into an output, wherein the output represents a MAC operation result of the inputs and the weights.