Semiconductor memory device
Abstract:
A semiconductor memory device includes a memory cell array including a plurality of memory cell transistors, a word line connected to a gate of each of the memory cell transistors, a sequencer configured to control an operation of the memory cell array, and an input/output circuit. When the input/output circuit receives a command instructing an operation of continuously reading data of a plurality of pages from the memory cell transistors, the sequencer determines the data of the plurality of pages by continuously applying read voltages corresponding to the plurality of pages to be read, to the word line. In each continuous time period during which the control circuit applies read voltages for determining the data of one of the pages to the word line, the control circuit does not apply any read voltage for determining the data of another one of the pages to the word line.
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