Invention Grant
- Patent Title: Isolation wall stressor structures to improve channel stress and their methods of fabrication
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Application No.: US17863292Application Date: 2022-07-12
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Publication No.: US12033896B2Publication Date: 2024-07-09
- Inventor: Aaron D. Lilak , Christopher J. Jezewski , Willy Rachmady , Rishabh Mehandru , Gilbert Dewey , Anh Phan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/78

Abstract:
In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.
Public/Granted literature
- US20220352029A1 ISOLATION WALL STRESSOR STRUCTURES TO IMPROVE CHANNEL STRESS AND THEIR METHODS OF FABRICATION Public/Granted day:2022-11-03
Information query
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