Invention Grant
- Patent Title: Semiconductor structures of anti-fuse devices and core devices with different dielectric layers and preparation method thereof
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Application No.: US17465099Application Date: 2021-09-02
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Publication No.: US12033938B2Publication Date: 2024-07-09
- Inventor: Xianlei Cao
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: CN 2110086754.3 2021.01.22
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/525 ; H01L23/532
Abstract:
A preparation method of the semiconductor structure includes: providing a substrate including a core device region and an anti-fuse device region; forming a first dielectric layer covering the core device region and the anti-fuse device region; forming a second dielectric layer covering the first dielectric layer and having a dielectric constant larger than a dielectric constant of the first dielectric layer; removing the second dielectric layer on the anti-fuse device region; and forming a conductive layer covering the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region.
Public/Granted literature
- US20220238437A1 SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREOF Public/Granted day:2022-07-28
Information query
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