Invention Grant
- Patent Title: Semiconductor package structure and method for forming the same
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Application No.: US17231310Application Date: 2021-04-15
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Publication No.: US12033947B2Publication Date: 2024-07-09
- Inventor: Chia-Kuei Hsu , Ming-Chih Yew , Shu-Shen Yeh , Po-Yao Lin , Shin-Puu Jeng
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/768

Abstract:
A semiconductor package structure includes a first bottom electrical connector, an interposer over the first bottom electrical connector, and a first top electrical connector over the first top via structures. The interposer includes first bottom via structures in contact with the first bottom electrical connector. The interposer also includes a first trace of a first redistribution layer structure over the first bottom via structures. The interposer also includes first via structures over the first redistribution layer. The interposer also includes a first trace of a second redistribution layer structure over the first via structures. The interposer also includes second via structures over the second redistribution layer structure. The first bottom via structures, the first via structures, and the second via structures are separated from each other in a top view.
Public/Granted literature
- US20220336359A1 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME Public/Granted day:2022-10-20
Information query
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