Invention Grant
- Patent Title: Double IO pad cell including electrostatic discharge protection scheme with reduced latch-up risk
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Application No.: US17702588Application Date: 2022-03-23
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Publication No.: US12034000B2Publication Date: 2024-07-09
- Inventor: Michael A. Stockinger , Mohamed Suleman Moosa
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H02H9/04

Abstract:
A double IO pad cell including a busing frame formed on a busing metal layer aligned with a same-sized component frame integrated on a component layer of an IC. The busing frame includes first and second IO pads, a supply voltage rail, and a ground voltage rail. The component frame includes first and second primary ESD circuitry each including a first diode coupled between a respective one of the first and second IO pads and the supply voltage rail and a second diode coupled between the respective IO pad and the ground voltage rail. The second diodes of each primary ESD circuitry are integrated adjacent each other sandwiched between the first diodes which act as collector guard bands for the second diodes. The diodes of each primary ESD circuitry of the component frame are aligned with a corresponding one of the first and second IO pads of the busing frame.
Public/Granted literature
- US20230307440A1 DOUBLE IO PAD CELL INCLUDING ELECTROSTATIC DISCHARGE PROTECTION SCHEME WITH REDUCED LATCH-UP RISK Public/Granted day:2023-09-28
Information query
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