Invention Grant
- Patent Title: Self-aligned metal gate with poly silicide for vertical transport field-effect transistors
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Application No.: US17133157Application Date: 2020-12-23
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Publication No.: US12034005B2Publication Date: 2024-07-09
- Inventor: Brent A. Anderson , Ruqiang Bao , Dechao Guo , Vijay Narayanan
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis LLP
- Agent Kimberly Zillig
- The original application number of the division: US15593816 2017.05.12
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H01L29/08 ; H01L29/66 ; H01L29/78

Abstract:
A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).
Public/Granted literature
- US20210118881A1 SELF-ALIGNED METAL GATE WITH POLY SILICIDE FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS Public/Granted day:2021-04-22
Information query
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