Invention Grant
- Patent Title: Reducing pattern loading in the etch-back of metal gate
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Application No.: US18298095Application Date: 2023-04-10
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Publication No.: US12034059B2Publication Date: 2024-07-09
- Inventor: Po-Chin Chang , Wei-Hao Wu , Li-Te Lin , Pinyen Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- The original application number of the division: US16035844 2018.07.16
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/8234 ; H01L21/8238 ; H01L29/49 ; H01L29/78

Abstract:
A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.
Public/Granted literature
- US20230246089A1 Reducing Pattern Loading in the Etch-Back of Metal Gate Public/Granted day:2023-08-03
Information query
IPC分类: