Invention Grant
- Patent Title: Hybrid node chiplet stacking design
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Application No.: US17752474Application Date: 2022-05-24
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Publication No.: US12039244B2Publication Date: 2024-07-16
- Inventor: Jen-Yuan Chang , Jheng-Hong Jiang , Chin-Chou Liu , Long Song Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06F30/27 ; G06F115/02 ; G06F115/12 ; G06F119/18

Abstract:
The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.
Public/Granted literature
- US20230041839A1 Hybrid Node Chiplet Stacking Design Public/Granted day:2023-02-09
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