Invention Grant
- Patent Title: Integrated circuit structure with a reduced amount of defects and methods for fabricating the same
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Application No.: US17462709Application Date: 2021-08-31
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Publication No.: US12040325B2Publication Date: 2024-07-16
- Inventor: Chia-Hao Pao , Chih-Hsuan Chen , Chih-Chuan Yang , Shih-Hao Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L29/40 ; H01L29/423 ; H01L29/66 ; H01L29/786

Abstract:
A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.
Public/Granted literature
- US20230061384A1 Integrated Circuit Structure with a Reduced Amount of Defects and Methods for Fabricating the Same Public/Granted day:2023-03-02
Information query
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