Invention Grant
- Patent Title: Methods and systems for controlling frequency variation for a PLL reference clock
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Application No.: US17732307Application Date: 2022-04-28
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Publication No.: US12040804B2Publication Date: 2024-07-16
- Inventor: YiTing Chen , Cindy Cheng , Hongquan Wang , Liang Chang , Kochung Lee
- Applicant: Parade Technologies, Ltd.
- Applicant Address: US CA San Jose
- Assignee: PARADE TECHNOLOGIES, LTD.
- Current Assignee: PARADE TECHNOLOGIES, LTD.
- Current Assignee Address: US CA San Jose
- Agency: Morgan, Lewis & Bockius LLP
- Main IPC: H03L7/089
- IPC: H03L7/089 ; G06F1/08 ; G06F1/10 ; G06F13/42 ; H03L7/083 ; H03L7/107

Abstract:
This application is directed to frequency controlling in an electronic device (e.g., a retimer of a data link). The electronic device includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal with reference to the input signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller determines whether the second reference signal is in a temporal range in which the second reference signal reaches a peak frequency and controls the selector to select the second reference signal as the input signal in accordance with a determination that the second reference signal is in the temporal range.
Public/Granted literature
- US20230350451A1 Methods and Systems for Controlling Frequency Variation for a PLL Reference Clock Public/Granted day:2023-11-02
Information query
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