Invention Grant
- Patent Title: Method for manufacturing buried word line transistor, transistor and memory
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Application No.: US17449502Application Date: 2021-09-30
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Publication No.: US12041764B2Publication Date: 2024-07-16
- Inventor: Gongyi Wu , Nan Deng , Yuchen Wang
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Syncoda LLC
- Agent Feng Ma
- Priority: CN 2010974520.8 2020.09.16
- Main IPC: H10B12/00
- IPC: H10B12/00

Abstract:
A method for manufacturing a buried word line transistor can include the following operations. A semiconductor substrate having an active region is provided. A first trench is formed in the active region. A first insulation layer is formed on a side wall of the first trench. A bottom portion of the first trench is etched to form a second trench. A gate oxide layer is formed on a side wall of the first insulation layer and a bottom portion and a side wall of the second trench. A barrier layer is formed at a bottom portion and portion of a side wall of the gate oxide layer. A metal filler layer is formed on an inner side of the barrier layer. The first insulation layer is removed to form a side trench. A second insulation layer is formed at a top end of the side trench. A sealed air spacer layer is formed.
Public/Granted literature
- US20220085031A1 METHOD FOR MANUFACTURING BURIED WORD LINE TRANSISTOR, TRANSISTOR AND MEMORY Public/Granted day:2022-03-17
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