Invention Grant
- Patent Title: Time and frequency domain side-channel leakage suppression using integrated voltage regulator cascaded with runtime crypto arithmetic transformations
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Application No.: US17132365Application Date: 2020-12-23
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Publication No.: US12047485B2Publication Date: 2024-07-23
- Inventor: Raghavan Kumar , Xiaosen Liu , Harish Krishnamurthy , Sanu Mathew , Vikram Suresh
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: NICHOLSON DE VOS WEBSTER & ELLIOTT LLP
- Main IPC: H04L9/00
- IPC: H04L9/00 ; G05F1/46 ; G05F1/575 ; G05F1/59 ; G06F1/26 ; H04L9/06 ; H04L9/08

Abstract:
Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.
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