An SRAM write controller of an arithmetic processing device for deep learning, which performs a convolution processing and a full-connect processing, virtually divides each SRAM constituting a data storage memory into a plurality of areas, switches the area to be written by the ID and controls so that different input feature maps of the same coordinate are stored in the same SRAM, and controls such that different input feature value map data of the same coordinate is stored in the same SRAM.