Transconductance amplifier of high linearity and common-mode rejection
Abstract:
A transconductance amplifier includes a first MOS transistor configured to receive a first voltage at a first node and output a first current to a fifth node in accordance with a third voltage at a third node; a second MOS transistor configured to receive a second voltage at a second node and output a second current to a sixth node in accordance with a fourth voltage at a fourth node; a third MOS transistor configured to output a third current to the third node in accordance with a fifth voltage at the fifth node; a fourth MOS transistor configured to output a fourth current to the fourth node in accordance with a sixth voltage at the sixth node; and a source degeneration network placed across the third node and the fourth node.
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