A semiconductor apparatus includes an internal clock generating circuit, a stop controlling circuit, and a data clock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a clock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.